VxWorks Reference Manual : Libraries
z8530Sio - Z8530 SCC Serial Communications Controller driver
z8530DevInit( ) - intialize a Z8530_DUSART
z8530IntWr( ) - handle a transmitter interrupt
z8530IntRd( ) - handle a reciever interrupt
z8530IntEx( ) - handle error interrupts
z8530Int( ) - handle all interrupts in one vector
This is the driver for the Z8530 SCC (Serial Communications Controller). It uses the SCCs in asynchronous mode only.
A Z8530_DUSART structure is used to describe the chip. This data structure contains two Z8530_CHAN structures which describe the chip's two serial channels. Supported baud rates range from 50 to 38400. The default baud rate is Z8530_DEFAULT_BAUD (9600). The BSP may redefine this.
The BSP's sysHwInit( ) routine typically calls sysSerialHwInit( ) which initializes all the values in the Z8530_DUSART structure (except the SIO_DRV_FUNCS) before calling z8530DevInit( ).
The BSP's sysHwInit2( ) routine typically calls sysSerialHwInit2( ) which connects the chips interrupts via intConnect( ) (either the single interrupt z8530Int or the three interrupts z8530IntWr, z8530IntRd, and z8530IntEx).
This driver handles setting of hardware options such as parity(odd, even) and number of data bits(5, 6, 7, 8). Hardware flow control is provided with the signals CTS on transmit and DSR on read. Refer to the target documentation for the RS232 port configuration. The function HUPCL(hang up on last close) is supported. Default hardware options are defined by Z8530_DEFAULT_OPTIONS. The BSP may redefine them.
All device registers are accessed via BSP-defined macros so that memory- mapped as well as I/O space accesses can be supported. The BSP may re- define the REG_8530_READ and REG_8530_WRITE macros as needed. By default, they are defined as simple memory-mapped accesses.
The BSP may define DATA_REG_8530_DIRECT to cause direct access to the Z8530 data register, where hardware permits it. By default, it is not defined.
The BSP may redefine the macro for the channel reset delay Z8530_RESET_DELAY as well as the channel reset delay counter value Z8530_RESET_DELAY_COUNT as required. The delay is defined as the minimum time between successive chip accesses (6 PCLKs + 200 nSec for a Z8530, 4 PCLKs for a Z85C30 or Z85230) plus an additional 4 PCLKs. At a typical PCLK frequency of 10 MHz, each PCLK is 100 nSec, giving a minimum reset delay of:
10 PCLKs + 200 nSec = 1200 nSec = 1.2 uSec
Z85x30: 8 PCLKs = 800 nSec = 0.8 uSec
drv/sio/z8530Sio.h
z8530DevInit( ) - intialize a Z8530_DUSART
void z8530DevInit ( Z8530_DUSART * pDusart )
The BSP must have already initialized all the device addresses, etc in Z8530_DUSART structure. This routine initializes some SIO_CHAN function pointers and then resets the chip to a quiescent state.
N/A
z8530IntWr( ) - handle a transmitter interrupt
void z8530IntWr ( Z8530_CHAN * pChan )
This routine handles write interrupts from the SCC.
N/A
z8530IntRd( ) - handle a reciever interrupt
void z8530IntRd ( Z8530_CHAN * pChan )
This routine handles read interrupts from the SCC.
N/A
z8530IntEx( ) - handle error interrupts
void z8530IntEx ( Z8530_CHAN * pChan )
This routine handles miscellaneous interrupts on the SCC.
N/A
z8530Int( ) - handle all interrupts in one vector
void z8530Int ( Z8530_DUSART * pDusart )
On some boards, all SCC interrupts for both ports share a single interrupt vector. This is the ISR for such boards. We determine from the parameter which SCC interrupted, then look at the code to find out which channel and what kind of interrupt.
N/A