VxWorks Reference Manual : Libraries
motCpmEnd - END style Motorola MC68EN360/MPC800 network interface driver
motCpmEndLoad( ) - initialize the driver and device
This module implements the Motorola MC68EN360 QUICC as well as the MPC821 and MPC860 Power-QUICC Ethernet Enhanced network interface driver.
All the above mentioned microprocessors feature a number of Serial Communication Controllers (SCC) that support different serial protocols including IEEE 802.3 and Ethernet CSMA-CD. As a result, when the Ethernet mode of a SCC is selected, by properly programming its general Mode Register (GSMR), they can implement the full set of media access control and channel interface functions those protocol require. However, while the MC68EN360 QUICC and the MPC860 Power-QUICC support up to four SCCs per unit, the MPC821 only includes two on-chip SCCs.
This driver is designed to support the Ethernet mode of a SCC residing on the CPM processor core, no matter which among the MC68EN360 QUICC or any of the PPC800 Series. In fact, the major differences among these processors, as far as the driver is concerned, are to be found in the mapping of the internal Dual-Port RAM. The driver is generic in the sense that it does not care which SCC is being used. In addition, it poses no constraint on the number of individual units that may be used per board. However, this number should be specified in the bsp through the macro MAX_SCC_CHANNELS. The default value for this macro in the driver is 4.
To achieve these goals, the driver requires several target-specific values provided as an input string to the load routine. It also requires some external support routines. These target-specific values and the external support routines are described below.
This network interface driver does not include support for trailer protocols or data chaining. However, buffer loaning has been implemented in an effort to boost performance.
This driver maintains cache coherency by allocating buffer space using the cacheDmaMalloc( ) routine. This is provided for boards whose host processor use data cache space, e.g. the MPC800 Series. Altough the MC68EN360 does not have cache memory, it may be used in a particular configuration: MC68EN360 in 040 companion mode where that is attached to processors that may cache memory. However, due to a lack of suitable hardware, the multiple unit support and '040 companion mode support have not been tested.
This device is on-chip. No jumpering diagram is necessary.
This driver provides the standard END external interface. The only external interface is the motCpmEndLoad( ) routine. The parameters are passed into the motCpmEndLoad( ) function as a single colon-delimited string. The motCpmEndLoad( ) function uses strtok( ) to parse the string, which it expects to be of the following format:
unit:motCpmAddr:ivec:sccNum:txBdNum:rxBdNum: txBdBase: rxBdBase:bufBase
- unit
- A convenient holdover from the former model. This parameter is used only in the string name for the driver.
- motCpmAddr
- Indicates the address at which the host processor presents its internal memory (also known as the dual ported RAM base address). With this address, and the SCC number (see below), the driver is able to compute the location of the SCC parameter RAM and the SCC register map, and, ultimately, to program the SCC for proper operations. This parameter should point to the internal memory of the processor where the SCC physically resides. This location might not necessarily be the Dual-Port RAM of the microprocessor configured as master on the target board.
- ivec
- This driver configures the host processor to generate hardware interrupts for various events within the device. The interrupt-vector offset parameter is used to connect the driver's ISR to the interrupt through a call to the VxWorks system function intConnect( ).
- sccNum
- This driver is written to support multiple individual device units. Thus, the multiple units supported by this driver can reside on different chips or on different SCCs within a single host processor. This parameter is used to explicitly state which SCC is being used (SCC1 is most commonly used, thus this parameter most often equals "1").
- txBdNum and rxBdNum
- Specify the number of transmit and receive buffer descriptors (BDs). Each buffer descriptor resides in 8 bytes of the processor's dual-ported RAM space, and each one points to a 1520 byte buffer in regular RAM. There must be a minimum of two transmit and two receive BDs. There is no maximum, although more than a certain amount does not speed up the driver and wastes valuable dual-ported RAM space. If any of these parameters is "NULL", a default value of "32" BDs is used.
- txBdBase and rxBdBase
- Indicate the base location of the transmit and receive buffer descriptors (BDs). They are offsets, in bytes, from the base address of the host processor's internal memory (see above). Each BD takes up 8 bytes of dual-ported RAM, and it is the user's responsibility to ensure that all specified BDs fit within dual-ported RAM. This includes any other BDs the target board might be using, including other SCCs, SMCs, and the SPI device. There is no default for these parameters. They must be provided by the user.
- bufBase
- Tells the driver that space for the transmit and receive buffers need not be allocated but should be taken from a cache-coherent private memory space provided by the user at the given address. The user should be aware that memory used for buffers must be 4-byte aligned and non-cacheable. All the buffers must fit in the given memory space. No checking is performed. This includes all transmit and receive buffers (see above). Each buffer is 1520 bytes. If this parameter is "NONE", space for buffers is obtained by calling cacheDmaMalloc( ) in motCpmEndLoad( ).
This driver requires three external support functions:
- sysXxxEnetEnable( )
This is either sys360EnetEnable( ) or sysCpmEnetEnable( ), based on the actual host processor being used. See below for the actual prototypes. This routine is expected to handle any target-specific functions needed to enable the Ethernet controller. These functions typically include enabling the Transmit Enable signal (TENA) and connecting the transmit and receive clocks to the SCC. This routine is expected to return OK on success, or ERROR. The driver calls this routine, once per unit, from the motCpmEndLoad( ) routine.
- sysXxxEnetDisable( )
This is either sys360EnetDisable( ) or sysCpmEnetDisable( ), based on the actual host processor being used. See below for the actual prototypes. This routine is expected to handle any target-specific functions required to disable the Ethernet controller. This usually involves disabling the Transmit Enable (TENA) signal. This routine is expected to return OK on success, or ERROR. The driver calls this routine from the motCpmEndStop( ) routine each time a unit is disabled.
- sysXxxEnetAddrGet( )
This is either sys360EnetAddrGet( ) or sysCpmEnetAddrGet( ), based on the actual host processor being used. See below for the actual prototypes. The driver expects this routine to provide the six-byte Ethernet hardware address that is used by this unit. This routine must copy the six-byte address to the space provided by addr. This routine is expected to return OK on success, or ERROR. The driver calls this routine, once per unit, from the motCpmEndLoad( ) routine.
In the case of the CPU32, the prototypes of the above mentioned support routines are as follows:
STATUS sys360EnetEnable (int unit, UINT32 regBase) void sys360EnetDisable (int unit, UINT32 regBase) STATUS sys360EnetAddrGet (int unit, u_char * addr)
In the case of the PPC860, the prototypes of the above mentioned support routines are as follows:
STATUS sysCpmEnetEnable (int unit) void sysCpmEnetDisable (int unit) STATUS sysCpmEnetAddrGet (int unit, UINT8 * addr)
When implemented, this driver requires the following system resources:
- one mutual exclusion semaphore
- one interrupt vector
- 0 bytes in the initialized data section (data)
- 1272 bytes in the uninitialized data section (BSS)The data and BSS sections are quoted for the CPU32 architecture and could vary for other architectures. The code size (text) varies greatly between architectures, and is therefore not quoted here.
If the driver allocates the memory to share with the Ethernet device unit, it does so by calling the cacheDmaMalloc( ) routine. For the default case of 32 transmit buffers, 32 receive buffers, and 16 loaner buffers (this is not configurable), the total size requested is 121,600 bytes. If a non-cacheable memory region is provided by the user, the size of this region should be this amount, unless the user has specified a different number of transmit or receive BDs.
This driver can operate only if this memory region is non-cacheable or if the hardware implements bus snooping. The driver cannot maintain cache coherency for the device because the buffers are asynchronously modified by both the driver and the device, and these fields might share the same cache line. Additionally, the chip's dual-ported RAM must be declared as non-cacheable memory where applicable (for example, when attached to a 68040 processor). For more information, see the Motorola MC68EN360 User's Manual , Motorola MPC860 User's Manual , Motorola MPC821 User's Manual
motCpmEndLoad( ) - initialize the driver and device
END_OBJ *motCpmEndLoad ( char * initString /* parameter string */ )
This routine initializes the driver and the device to the operational state. All of the device specific parameters are passed in the initString, which is of the following format:
unit:motCpmAddr:ivec:sccNum:txBdNum:rxBdNum:txBdBase:rxBdBase:bufBase
The parameters of this string are individually described in the motCpmEnd man page.
The SCC shares a region of memory with the driver. The caller of this routine can specify the address of a non-cacheable memory region with bufBase. Or, if this parameter is "NONE", the driver obtains this memory region by making calls to cacheDmaMalloc( ). Non-cacheable memory space is important whenever the host processor uses cache memory. This is also the case when the MC68EN360 is operating in companion mode and is attached to a processor with cache memory.
After non-cacheable memory is obtained, this routine divides up the memory between the various buffer descriptors (BDs). The number of BDs can be specified by txBdNum and rxBdNum, or if "NULL", a default value of 32 BDs will be used. An additional number of buffers are reserved as receive loaner buffers. The number of loaner buffers is a default number of 16.
The user must specify the location of the transmit and receive BDs in the processor's dual ported RAM. txBdBase and rxBdBase give the offsets from motCpmAddr for the base of the BD rings. Each BD uses 8 bytes. Care must be taken so that the specified locations for Ethernet BDs do not conflict with other dual ported RAM structures.
Multiple individual device units are supported by this driver. Device units can reside on different chips, or could be on different SCCs within a single processor. The sccNum parameter is used to explicitly state which SCC is being used. SCC1 is most commonly used, thus this parameter most often equals "1".
Before this routine returns, it connects up the interrupt vector ivec.
An END object pointer or NULL on error.
motCpmEnd, Motorola MC68EN360 User's Manual , Motorola MPC860 User's Manual , Motorola MPC821 User's Manual