VxWorks Reference Manual : Libraries
cacheTiTms390Lib - TI TMS390 SuperSPARC cache management library
cacheTiTms390LibInit( ) - initialize the TI TMS390 cache library
cacheTiTms390VirtToPhys( ) - translate a virtual address for cacheLib
cacheTiTms390PhysToVirt( ) - translate a physical address for drivers
cleanUpStoreBuffer( ) - clean up store buffer after a data store error interrupt
This library contains architecture-specific cache library functions for the TI TMS390 SuperSPARC architecture. The on-chip cache architecture is explained in the first table below. Note, the data cache mode depends on whether there is an external Multicache Controller (MCC). Both on-chip caches support cache coherency via snooping and line locking. For memory allocation purposes, a cache line alignment size of 64 bytes is assumed. The MCC supports cache coherency via snooping, but does not support line locking.
The cache operations provided are explained in the table below. Operations marked "Hardware" and "Software" are implemented as marked, and are fast and slow, respectively. Operations marked "NOP" return OK without doing anyting. Operations with another operation name perform that operation rather than their own. Partial operations marked "Entire" actually perform an "Entire" operation. When the MCC is installed, operations upon the data cache are performed upon both the data cache and the MCC. Lines "Data-Data" and "Data-MCC" desribe the data cache and MCC, respectively, portions of a data cache operation.
Cache Line Size Type Size Lines Sets Ways (Bytes) Mode Instr 20K 320 64 5 2*32 never written back Data 16K 512 128 4 32 with MCC: Write-through without MCC: Copy-back with write allocation
The architecture of the optional Multicache Controller (MCC) is explained in the table below. The MCC supports cache coherency via snooping, and does not support line locking.
MCC: No No Yes Yes Yes Cache Type: Instr Data Instr Data-Data Data-MCC cacheInvalidate( ) entire H/W H/W H/W H/W S/W partial Entire S/W Entire S/W S/W cacheFlush( ) entire NOP Clear NOP NOP S/W partial NOP Clear NOP NOP Clear cacheClear( ) entire H/W S/W H/W H/W S/W partial Entire S/W Entire S/W S/W cacheLock( ) and entire S/W S/W S/W S/W NOP cacheUnlock( ) partial S/W S/W S/W S/W NOP The MCC does not have a CACHE_TYPE value for cacheEnable( ) or cacheDisable( ). For enable and disable operations, the MCC is treated as an extension of both the on-chip data and instruction caches. If either the data or instruction caches are enabled, the MCC is enabled. If both the data and the instruction caches are disabled, the MCC is disabled. For invalidate, flush, and clear operations the MCC is treated as an extension of only the on-chip data cache. The cacheInvalidate( ), cacheFlush( ), and cacheClear( ) operations for the instruction cache operate only on the on-chip instruction cache. However these operations for the data cache operate on both the on-chip data cache and the MCC.
Any input peripheral that does not support cache coherency cay be accessed through either a cached buffer with a partial cacheTiTms390Invalidate( ) operation, or an uncached buffer without it. (cacheInvalidate( ) cannot be used; it is a NOP since it assumes cache coherency.) Choose whichever is faster for the application.
Block Size Cache Type Size Blocks Ways (bytes) Mode MCC on MBus 0, 1M 0, 8K 1 4*32 Copy-back MCC on XBus 512K, 1M, 2M 2K, 4K, 8K 1 4*64 Copy-back Any output peripheral that does not support cache coherency may be accessed through either a cached buffer with a partial cacheTiTms390Flush( ) operation, or an uncached buffer without it. (cacheFlush( ) cannot be used; it is a NOP since it assumes cache coherency.) Choose whichever is faster for the application.
Any peripheral that supports cache coherency should be accessed through a cached buffer without using any of the above operations. Using either an uncached buffer or any of the above operations will just slow the system down.
MMU (Memory Management Unit) support is needed to mark pages cacheable or non-cacheable. For more information, see the manual entry for vmLib.
For general information about caching, see the manual entry for cacheLib.
cacheLib.h
cacheTiTms390Lib, cacheLib, vmLib
cacheTiTms390LibInit( ) - initialize the TI TMS390 cache library
STATUS cacheTiTms390LibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )
This routine initializes the function pointers for the TI TMS390 cache library. The board support package can select this cache library by assigning the function pointer sysCacheLibInit to cacheTiTms390LibInit( ).
The only available cache mode is CACHE_COPYBACK.
OK, or ERROR if cache control is not supported.
cacheTiTms390VirtToPhys( ) - translate a virtual address for cacheLib
void * cacheTiTms390VirtToPhys ( void * address /* virtual address */ )
This routine performs a 32-bit virtual to 32-bit physical address translation in the current context.
The physical address translation bits [31:0] of a virtual address argument, or NULL if the virtual address is not valid, or the physical address does not fit in 32 bits.
N/A
cacheTiTms390PhysToVirt( ) - translate a physical address for drivers
void * cacheTiTms390PhysToVirt ( void * address /* physical address */ )
This routine performs a 32-bit physical to 32-bit virtual address translation in the current context.
It works for only DRAM addresses of the first EMC.
It guesses likely virtual addresses, and checks its guesses with VM_TRANSLATE. A likely virtual address is the same as the physical address, or some multiple of 16M less. If any match, it succeeds. If all guesses are wrong, it fails.
The virtual address that maps to the physical address bits [31:0] argument, or NULL if it fails.
N/A
cleanUpStoreBuffer( ) - clean up store buffer after a data store error interrupt
void cleanUpStoreBuffer ( UINT mcntl, /* Value of MMU Control Register */ BOOL exception /* TRUE if exception, FALSE if int */ )
This routine cleans up the store buffer after a data store error interupt. The first queued store is retried. It is logged as either a recoverable or unrecoverable error. Then the store buffer is re-enabled and other queued stores are processed by the store buffer.
N/A