VxWorks Reference Manual : Libraries
cacheMicroSparcLib - microSPARC cache management library
cacheMicroSparcLibInit( ) - initialize the microSPARC cache library
This library contains architecture-specific cache library functions for the microSPARC architecture. Currently two microSPARC CPU are supported: the Texas Instrument TMS3900S10 (also known as Tsunami) and the FUJITSU MB86904 (also know as Swift). The TMS390S10 implements a 4-Kbyte Instruction and a 2-Kbyte Data cache, the MB86904 a 16-Kbyte Instruction and a 8-Kbyte Data cache. Both operate in write-through mode. The Instruction Cache Line size is 32 bytes while the Data Cache Line size is 16 bytes, but for memory allocation purposes, a cache line alignment size of 32 bytes will be assumed. The TMS390S10 either cache only supports invalidation of all entries and no cache locking is available, the MB86904 supports a per cache line invalidation, with specific alternate stores, but no cache locking
MMU (Memory Management Unit) support is needed to mark pages cacheable or non-cacheable. For more information, see the manual entry for vmLib.
For general information about caching, see the manual entry for cacheLib.
cacheLib.h
cacheMicroSparcLib, cacheLib, vmLib
cacheMicroSparcLibInit( ) - initialize the microSPARC cache library
STATUS cacheMicroSparcLibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )
This routine initializes the function pointers for the microSPARC cache library. The board support package can select this cache library by assigning the function pointer sysCacheLibInit to cacheMicroSparcLibInit( ).
The only available cache mode is CACHE_WRITETHROUGH.
OK, or ERROR if cache control is not supported.