VxWorks Reference Manual : Libraries
cacheI960CxALib - I960Cx cache management assembly routines
cacheI960CxICDisable( ) - disable the I960Cx instruction cache (i960)
cacheI960CxICEnable( ) - enable the I960Cx instruction cache (i960)
cacheI960CxICInvalidate( ) - invalidate the I960Cx instruction cache (i960)
cacheI960CxICLoadNLock( ) - load and lock I960Cx 512-byte instruction cache (i960)
cacheI960CxIC1kLoadNLock( ) - load and lock I960Cx 1KB instruction cache (i960)
This library contains Intel I960Cx cache management routines written in assembly language. The I960CX utilize a 1KB instruction cache and no data cache.
For general information about caching, see the manual entry for cacheLib.
cacheLib.h
cacheI960CxALib, cacheI960CxLib, cacheLib, I960Cx Processors User's Manual
cacheI960CxICDisable( ) - disable the I960Cx instruction cache (i960)
void cacheI960CxICDisable (void)
This routine disables the I960Cx instruction cache.
N/A
cacheI960CxICEnable( ) - enable the I960Cx instruction cache (i960)
void cacheI960CxICEnable ( void )
This routine enables the I960Cx instruction cache.
N/A
cacheI960CxICInvalidate( ) - invalidate the I960Cx instruction cache (i960)
void cacheI960CxICInvalidate ( void )
cacheI960CxICLoadNLock( ) - load and lock I960Cx 512-byte instruction cache (i960)
void cacheI960CxICLoadNLock ( void * address )
This routine loads and locks the I960Cx 512-byte instruction cache. The loaded address must be an address of a quad-word aligned block of memory. The instructions loaded into the cache can only be accessed by selected interrupts which vector to the addresses of these instructions. The load-and-lock mechanism selectively optimizes latency and throughput for interrupts.
N/A
cacheI960CxIC1kLoadNLock( ) - load and lock I960Cx 1KB instruction cache (i960)
void cacheI960CxIC1kLoadNLock ( void * address )
This routine loads and locks the I960Cx 1KB instruction cache. The loaded address must be an address of a quad-word aligned block of memory. The instructions loaded into the cache can only be accessed by selected interrupts which vector to the addresses of these instructions. The load-and-lock mechanism selectively optimizes latency and throughput for interrupts.
N/A