VxWorks Reference Manual : Libraries
cacheArchLib - architecture-specific cache management library
cacheArchLibInit( ) - initialize the cache library
cacheArchClearEntry( ) - clear an entry from a cache (68K, x86)
cacheStoreBufEnable( ) - enable the store buffer (MC68060 only)
cacheStoreBufDisable( ) - disable the store buffer (MC68060 only)
This library contains architecture-specific cache library functions for the following processor cache families: Motorola 68K, Intel 960, Intel x86, PowerPC, ARM, and the Solaris, HP-UX, and NT simulators. Each routine description indicates which architecture families support it. Within families, different members support different cache mechanisms; thus, some operations cannot be performed by certain processors because they lack particular functionalities. In such cases, the routines in this library return ERROR. Processor-specific constraints are addressed in the manual entries for routines in this library. If the caches are unavailable or uncontrollable, the routines return ERROR. The exception to this rule is the 68020; although the 68020 has no cache, data cache operations return OK.
The SPARC and MIPS archetecture families have cache-related routines in individual BSP libraries. See the reference pages for the individual libraries and routines.
cacheLib.h, mmuLib.h (ARM only)
cacheArchLibInit( ) - initialize the cache library
STATUS cacheArchLibInit ( CACHE_MODE instMode, /* instruction cache mode */ CACHE_MODE dataMode /* data cache mode */ )
This routine initializes the cache library for the following processor cache families: Motorola 68K, Intel 960, Intel x86, PowerPC ARM, and the Solaris, HP-UX, and NT simulators. It initializes the function pointers and configures the caches to the specified cache modes.
The caching modes vary for members of the 68K processor family:
The write-through, copy-back, serial, non-serial, precise and non precise modes change the state of the data transparent translation register (DTTR0) CM bits. Only DTTR0 is modified, since it typically maps DRAM space.
68020
CACHE_WRITETHROUGH (instruction cache only) 68030
CACHE_WRITETHROUGH CACHE_BURST_ENABLE CACHE_BURST_DISABLE CACHE_WRITEALLOCATE (data cache only) CACHE_NO_WRITEALLOCATE (data cache only) 68040
CACHE_WRITETHROUGH CACHE_COPYBACK (data cache only) CACHE_INH_SERIAL (data cache only) CACHE_INH_NONSERIAL (data cache only) CACHE_BURST_ENABLE (data cache only) CACHE_NO_WRITEALLOCATE (data cache only) 68060
CACHE_WRITETHROUGH CACHE_COPYBACK (data cache only) CACHE_INH_PRECISE (data cache only) CACHE_INH_IMPRECISE (data cache only) CACHE_BURST_ENABLE (data cache only)
The caching mode CACHE_WRITETHROUGH is available for the x86 processor family.
Modes should be set before caching is enabled. If two contradictory flags are set (for example, enable/disable), no action is taken for any of the input flags.
The caching capabilities and modes vary for members of the ARM processor family. All caches are provided on-chip, so cache support is mostly an architecture issue, not a BSP issue. However, the memory map is BSP-specific and some functions need knowledge of the memory map, so they have to be provided in the BSP.
- ARM7TDMI (In ARM or Thumb state)
- No cache or MMU at all. Dummy routine provided, so that INCLUDE_CACHE_SUPPORT can be defined (the default BSP configuration).
- ARM710A
- Combined instruction and data cache. Actually a write-through cache, but separate write-buffer effectively makes this a copy-back cache if the write-buffer is enabled. Use write-through/copy-back argument to decide whether to enable write buffer. Data and instruction cache modes must be identical.
- ARM810
- Combined instruction and data cache. Write-through and copy-back cache modes, but separate write-buffer effectively makes even write-through a copy-back cache as all writes are buffered, when cache is enabled. Data and instruction cache modes must be identical.
- ARMSA110
- Separate instruction and data caches. Write-through and copy-back cache mode for data, but separate write-buffer effectively makes even write-through a copy-back cache as all writes are buffered, when cache is enabled.
OK
cacheArchClearEntry( ) - clear an entry from a cache (68K, x86)
STATUS cacheArchClearEntry ( CACHE_TYPE cache, /* cache to clear entry for */ void * address /* entry to clear */ )
This routine clears a specified entry from the specified cache.
For 68040 processors, this routine clears the cache line from the cache in which the cache entry resides.
For the MC68060 processor, when the instruction cache is cleared (invalidated) the branch cache is also invalidated by the hardware. One line in the branch cache cannot be invalidated so each time the branch cache is entirely invalidated.
For 386 processors and PENTIUMPRO processors with SNOOP_ENABLED data cache mode, this routine does nothing.
OK, or ERROR if the cache type is invalid or the cache control is not supported.
cacheStoreBufEnable( ) - enable the store buffer (MC68060 only)
void cacheStoreBufEnable (void)
This routine sets the ESB bit of the Cache Control Register (CACR) to enable the store buffer. To maximize performance, the four-entry first-in-first-out (FIFO) store buffer is used to defer pending writes to writethrough or cache-inhibited imprecise pages.
N/A
cacheStoreBufDisable( ) - disable the store buffer (MC68060 only)
void cacheStoreBufDisable (void)
This routine resets the ESB bit of the Cache Control Register (CACR) to disable the store buffer.
N/A